Encoding techniques for achieving reduction of power dissipation and delay by reducing BIT transitions and crosstalk on the buses for low power VLSI: thesis / (Record no. 136011)

000 -LEADER
fixed length control field 00633nam a22001457a 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 200608b ||||| |||| 00| 0 eng d
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number PHD 621.3815
Item number P18/SHA
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Shankaranarayana Bhat M
245 ## - TITLE STATEMENT
Title Encoding techniques for achieving reduction of power dissipation and delay by reducing BIT transitions and crosstalk on the buses for low power VLSI: thesis /
Statement of responsibility, etc. M Shankaranarayana Bhat
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc. Mangalagangothri:
Name of publisher, distributor, etc. Mangalore University,
Date of publication, distribution, etc. 2018.
300 ## - PHYSICAL DESCRIPTION
Extent v, 129p.;
Other physical details 29.5 cm.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Physics - thesis |
-- Integrated circuits - thesis |
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Balakrishna K M
Relator term Research guide
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Thesis
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Permanent location Current location Shelving location Date acquired Full call number Barcode Date last seen Price effective from Koha item type
          Mangalore University Library Mangalore University Library Reference 2020-06-08 PHD 621.3815 P18/BHA D1365 2020-06-08 2020-06-08 Thesis

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