Shankaranarayana Bhat M
Encoding techniques for achieving reduction of power dissipation and delay by reducing BIT transitions and crosstalk on the buses for low power VLSI: thesis / M Shankaranarayana Bhat - Mangalagangothri: Mangalore University, 2018. - v, 129p.; 29.5 cm.
Physics - thesis |
Integrated circuits - thesis |
PHD 621.3815 / P18/SHA
Encoding techniques for achieving reduction of power dissipation and delay by reducing BIT transitions and crosstalk on the buses for low power VLSI: thesis / M Shankaranarayana Bhat - Mangalagangothri: Mangalore University, 2018. - v, 129p.; 29.5 cm.
Physics - thesis |
Integrated circuits - thesis |
PHD 621.3815 / P18/SHA