000			00633nam a22001457a 4500
999			_c136011 _d136011
008			200608b ||||| |||| 00| 0 eng d
082			_aPHD 621.3815 _bP18/SHA
100			_aShankaranarayana Bhat M
245			_aEncoding techniques for achieving reduction of power dissipation and delay by reducing BIT transitions and crosstalk on the buses for low power VLSI: thesis / _cM Shankaranarayana Bhat
260			_aMangalagangothri: _bMangalore University, _c2018.
300			_av, 129p.; _b29.5 cm.
650			_aPhysics - thesis | _aIntegrated circuits - thesis |
700			_aBalakrishna K M _eResearch guide
942			_cD